`timescale 1ns/1ns
interface PR_if(input bit sys_clk); 
 
parameter aw = 5;
parameter dw = 32;

bit                rst_n;
bit                DSP_core_en;
bit        [aw-1:0]PW_PC;
bit        [aw-1:0]PR_PC;
bit        [dw-1:0]Fet_Pkt_i;
bit        [dw-1:0]Fet_Pkt_o;
bit                DP_stall;
bit                I_FP_invalid;
bit                D_RAM_invalid;

bit                PW_io_invalid;
bit                PR_io_invalid;  
bit                FP_stall;
  
bit                Int_Sev;   


//********************************************************************************************************************* 


clocking cb @(negedge sys_clk);
output                   rst_n,
                         PW_PC,
                         Fet_Pkt_i,
                         DP_stall,
                         I_FP_invalid,
                         D_RAM_invalid,
                         PW_io_invalid,
                         Int_Sev,
                         DSP_core_en;
                          
input                    PR_PC, 
                         Fet_Pkt_o, 
                         PR_io_invalid, 
                         FP_stall;
endclocking 


//*********************************************************************************************************************   
  

  modport TEST (clocking cb );

  modport DUT (input     rst_n,
                         PW_PC,
                         Fet_Pkt_i,
                         DP_stall,
                         I_FP_invalid,
                         D_RAM_invalid,
                         PW_io_invalid,
                         Int_Sev,
                         DSP_core_en,
               output    PR_PC, 
                         Fet_Pkt_o,
                         PR_io_invalid, 
                         FP_stall );

  modport MONITOR (input sys_clk,
                         rst_n,
                         PW_PC,
                         Fet_Pkt_i,
                         DP_stall,
                         I_FP_invalid,
                         D_RAM_invalid,
                         PW_io_invalid,
                         Int_Sev,
                         DSP_core_en,
                         PR_PC, 
                         Fet_Pkt_o,
                         PR_io_invalid, 
                         FP_stall  );

endinterface
